SL83115
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SL83115

SL83115 is a MIPI D-PHY de-serializer which supports a D-PHY bandwidth of up to 4 Gbps. It is designed to be used together with Silicon Line's VCSEL drivers and TIAs to create a complete optical link but can also be used to transport the serialized data electrically.

Categories:

Features

  • De-serializes up to 4 MIPI D-PHY data lanes together with the MIPI D-PHY clock lane
  • Supports lane data rates of up to 2 Gbps per lane in 2 lane mode and up to 1 Gbps in 4 lane mode
  • Dual clock output for stereo camera applications
  • Can de-serialize an additional 6 general purpose CMOS level signals
  • Can also be used for HiSPi camera applications
  • Ultra-low power consumption of 42 mW at the maximum data rate
  • Available in a QFN-48 package

Applications

  • Optical / electrical links for MIPI D-PHY interfaces in smart phones, tablets, notebooks and TVs using the CSI-2 or DSI protocol
  • Optical / electrical links for HiSPi camera applications
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