SL83115
Categories:
Features
- De-serializes up to 4 MIPI D-PHY data lanes together with the MIPI D-PHY clock lane
- Supports lane data rates of up to 2 Gbps per lane in 2 lane mode and up to 1 Gbps in 4 lane mode
- Dual clock output for stereo camera applications
- Can de-serialize an additional 6 general purpose CMOS level signals
- Can also be used for HiSPi camera applications
- Ultra-low power consumption of 42 mW at the maximum data rate
- Available in a QFN-48 package
Applications
- Optical / electrical links for MIPI D-PHY interfaces in VR / AR, medical and security applications
- Optical / electrical links for HiSPi camera applications